Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured.
Presently, pre-packaged circuit designs are available for FPGAs, which are referred to as intellectual property cores (IP cores). IP cores typically provide sub-circuits or “modules” that operate in accordance with established specifications (e.g., in accordance with particular timing). IP cores allow a user of an FPGA to generate a design more quickly and with fewer bugs. Thus, users are willing to pay for IP cores to speed up their design process. As the complexity of IP cores has increased, so has the required investment in labor and finances by the designers that create them. Given their increased complexity, expense, and value, it is desirable to protect them from unauthorized use.
Currently, designers bundle and license IP cores to users. Once a license is granted, a user is able to instantiate the IP core logic into his or her design and may at this point visualize the implementation. This IP core in the design is then identical to any other logic that can be analyzed by design tools. Thus, the user is free to slightly modify a licensed IP core that may then be freely shared with other users. To an IP core designer, this distribution of modified IP cores is lost revenue. Accordingly, there exists a need in the art for generating IP cores in a secure form that cannot be visualized or modified by users.